1. Field of the Invention
The present invention relates to a digital filtering circuit for filtering digital data and more specifically to a digital filtering circuit suitable for filtering an inputted digital video signal in which a luminance signal and color-difference signals are multiplexed in unit of byte (8 bits). The invention also relates to a digital filtering circuit for processing the digital video signal suitably formed in a semiconductor integrated circuit device.
2. Description of the Related Art
A coding format called ITU-R (International Telecommunication Unionxe2x80x94Radio communication) Recommendation BT. 601 (hereinafter referred to as BT. 601) is used often in general as an input format of a digital video signal. Recommendation BT. 601 will be explained below.
Utilizing the fact that the human is not so sensitive to colors, Recommendation BT. 601 reduces color information to a half in the horizontal direction. Sampling frequency of a luminance signal Y is set at 13.5 MHz and sampling frequency of two color-difference signals Cb and Cr is set at 6.75 MHz, i.e., a half of the former. Accordingly, the ratio of the sampling frequencies of the luminance signal Y, the color-difference signal Cb and the color-difference signal Cr is 4:2:2. From this point, this format is called a 4:2:2 coding system or a 4:2:2 digital component signal. Here, the luminance signal Y, the color-difference signal Cb and the color-difference signal Cr are digital data of 8 bits, respectively, per one pixel. That is, the quantizing accuracy is 8 bits. It is noted that when primary color signals are R (red), G (green) and B (blue), the color-difference signal Cb is a digital signal of a difference (Bxe2x88x92Y) and the color-difference signal Cr is a digital signal of a difference (Rxe2x88x92Y). Although a 4:4:4 coding system and a system in which quantizing accuracy of each of the signals Y, Cb and Cr is set at 10 bits are also stipulated in the format of BT. 601, the 8bit 4:2:2 system which is widely used in general will be explained below.
FIG. 7 shows an outline of the format of Recommendation BT. 601. In BT. 601, data are lined in order of pixel 0, 1, 2, . . . from the left of the screen until 719. Among them, data of the color-difference signals Cb and Cr exist for the pixels affixed with even numbers (0, 2, 4, . . . 718). When the luminance signal Y and the color-difference signals Cb and Cr of a pixel n are represented by Yn, Cbn and Crn, respectively, the data turns out to be a data string in which the luminance signal Y is inserted (interleaved) every other data (per two periods) and the color-difference signals Cb and Cr are inserted every three data (per four periods) regularly in the horizontal direction like Cb0, Y0, Cr0, Y1, Cb2, Y2, Cr2, Y3, . . . In other words, the luminance signal Y and the color-difference signals Cb and Cr may be considered to be multiplexed. The data is transmitted in synchronism with a transmission clock of 27 MHz in line in the horizontal direction in order from the smaller line number (in order of pixel 0, 1, 2, . . . ). Accordingly, the data string or the data stream of Recommendation BT. 601 is a data string or a data stream in which the luminance signals Y, color-difference signals Cb and Cr are interleaved respectively in unit of 8 bits and which is synchronized with the clock of 27 MHz.
It is noted that there is a case when a filtering process is implemented to the digital video signal inputted in the format of the above-mentioned Recommendation BT. 601 for the purpose of removing noises and of restricting a band in systems handling the digital video signal such as a digital broadcasting receiver, a digital camera and a video phone.
A case of implementing a filtration operation on the data string of Recommendation BT. 601 by a known transversal filter in the horizontal direction will be explained below.
It is noted that although the transversal filter itself is known, the structure of a digital filtering circuit shown in FIGS. 2 and 4, i.e., a combination circuit of the transversal filter and a timing operation explained in FIGS. 3 and 5 are not publicly known and are a digital filtering circuit and its timing operation discussed by the inventors in the process of devising the present invention.
In implementing the filtration operation by the transversal filter, it is conceivable of implementing the filtering process in the independent digital filtering circuits respectively after separating the luminance signal Y and the two color-difference signals Cb and Cr from the data string in which the luminance signals and the color-difference signals are multiplexed.
FIG. 2 shows the structure of the digital filtering circuit in performing filtration operations of three taps. In the digital filtering circuit in FIG. 2, filtration operating sections of the luminance signal Y and the color-difference signals Cb and Cr are formed independently from each other. Each of the filtration operating sections 201, 202 and 203 which are set as the transversal filter comprises a delay line composed of three D flip-flops 10, three multipliers 30, 31 and 32 for multiplying the three taps of the delay line by adequate tap coefficients a0, a1 and a2 and an adder 40 for adding and outputting the result of the three multipliers. It is noted that each D flip-flop 10 is a D flip-flop of 8 bits and latches input data at the rising edge of clocks clk2, clk3 and clk4 to be supplied.
The D flip-flop 10 at the input stage of each of the filtration operating sections 201, 202 and 203 separates data from an input node IN by receiving clocks clk2, clk3 and clk4 which are generated by a clock generator circuit 60 described later and which are different from each other.
FIG. 3 is a timing chart of the clock input and output data d0, d1 and d2 of the D flip-flop 10 on each input stage. The clock clk2 of 13.5 MHz is used for the luminance signal Y and the clocks clk3 and clk4 of 6.75 MHz are used for the color-difference signals Cb and Cr, respectively, as the clock inputted to the input stage D flip-flop 10. These clocks clk2, clk3 and clk4 are generated by the clock generator circuit 60 based on a clock clk1 of 27 MHz which is synchronism with the data string of BT. 601 inputted from the input node IN. As shown in the time chart in FIG. 3, the data string inputted from the input node IN may be separated into data strings of the luminance signal Y, the color-difference signal Cb and the color-difference signal Cr like the output data d0, d1 and d2, respectively, and the filtering operation may be implemented independently by latching at the rising edge of the clocks clk2, clk3 and clk4.
Next, a digital filtering circuit in filtering in two directions of the horizontal and vertical directions will be explained. FIG. 4 shows the structure of the digital filtering circuit in implementing the filtering process of three taps both in the horizontal and vertical directions as an example. This digital filtering circuit will be explained below.
The digital filtering circuit in FIG. 4 is what a filtration operating section comprising a horizontal direction filtering section and a vertical direction filtering section is structured for the luminance signal Y, the color-difference signal Cb and the color-difference signal Cr independently from each other. The configuration of the horizontal direction filtering section HF is equal to that of the digital filtering circuit in FIG. 2. The vertical direction filtering section VF comprises a delay line composed of two line memories, three multipliers 33, 34 and 35 for multiplying three taps of the delay line by tap coefficients, respectively, and an adder 41 for adding outputs of the three multipliers in each filtration operating section.
Each line memory is a FIFO (First In First Out) memory and has a data capacity of one line of data string to be processed in each of the filtration operating sections 401, 402 and 403. That is, line memories 50a and 50b of the filtration operating section 401 of the luminance signal Y has 720 bytes corresponding to a number of pixels of one line and line memories 51a and 51b of the filtration operating sections 402 and 403 of the color-difference signals Cb and Cr have 360 bytes which is a half of the number of pixels of one line, respectively. The filtration operating section 401 of the luminance signal Y will be exemplified below to explain the operation of the digital filtering circuit in FIG. 4.
The filtration operating section 401 of the luminance signal Y separates the data string of the luminance signal Y from the interleaved data string by the D flip-flop 10 at the input stage in the horizontal direction filtering section HF at first and performs the filtering process of the three taps in the horizontal direction on the data string of the luminance signal Y. That is, the multipliers 30, 31 and 32 multiply the Y data of the respective taps delayed by each flip-flop 10 by the tap coefficient and the adder 40 adds the results of the multiplication and outputs as the result of the filtering process in the horizontal direction. The output of the filtration of the horizontal direction filtering section HF is sent to the line memory 50a. Output data LM1 of the line memory 50a becomes data of the luminance signal Y of a pixel of input data LM0 of the line memory 50a of one line before. Similarly to that, an output LM2 of the second line memory 50b becomes data of the luminance signal Y of a pixel of the input data LM1 of the line memory 50b of one line before. Accordingly, the data LM0, LM1 and LM2 become data of the luminance signal Y of the pixels continued in the vertical direction.
In the vertical direction filtering section VF, these data LM0, LM1 and LM2 are set as three taps of the filter, the multipliers 33, 34 and 35 multiply the respective taps by tap coefficients and the adder 41 adds the results of the multiplication. An output of the adder 41 becomes an output of filtration of the filtration operating section 401. It is the same also in each of the filtration operating sections 402 and 403 of the color-difference signals Cb and Cr. That is, the filtration operation may be implemented in the horizontal and vertical directions for the respective data of the luminance signal Y, the color-difference signal Cb and the color-difference signal Cr in the digital filtering circuit shown in FIG. 4.
However, the digital filtering circuits having the configurations as shown in FIGS. 2 and 4 comprise the three filtration operating sections having the same structure independently with respect to each data string of the luminance signal Y, the color-difference signal Cb and the color-difference signal Cr. Therefore, a number of the multipliers in one filtration operating section becomes large in a digital filtering circuit having a large number of taps and along that, a circuit scale of the adder for adding the multiplication results becomes large. It has been clarified by the study conducted by the inventor that when the circuit scale of one filtration operating section is large as such, the circuit scale of the whole digital filtering circuit which is three times of that becomes enormous.
Accordingly, when the digital filtering circuit constructed as described above is formed within a semiconductor integrated circuit device, an area on a semiconductor chip occupied by the digital filtering circuit has been widened and it has been difficult to lower the cost of the semiconductor integrated circuit device as a result.
It is an object of the present invention to provide a digital filtering circuit whose circuit scale is small and which is suitable for filtering a digital video signal.
It is another object of the invention to provide a digital filtering circuit for processing a digital video signal whose circuit scale is small so that it is suitably formed within a semiconductor integrated circuit device.
An outline of typical ones of the invention disclosed in the present application may be explained as follows.
That is, a digital filtering circuit of a first configuration of the invention is a filtering circuit for filtering a data string or a data stream in which data of a plurality of data string or data stream elements are regularly and periodically inserted or multiplexed. The digital filtering circuit of the first configuration of the invention comprises a delay line composed of at least (f1/f2)xe2x88x92(Nxe2x88x921) D flip-flops, where f1 is transmission frequency of the data string, f2 is transmission frequency of a data string element whose transmission frequency is least among the data string elements contained in the data string and N is a number of taps; a plurality of multipliers for multiplying the plurality of taps of the delay line by respective coefficients; and an adder for adding outputs of the multipliers; wherein the delay line is operated with the transmission frequency f1 of the data string and there is provided means for processing the plurality of data string elements in a time division manner.
For instance, the delay line is composed of eight D flip-flops when the transmission frequency fl of the data string is in the relationship of f1=27 MHz, the least transmission frequency f2 of the data string element is in the relationship of f2=6.75 MHz and the number of taps N=3.
A digital filtering circuit of a second configuration of the invention is a filtering circuit for filtering a data string in which data of a plurality of data string elements in which transmission frequency of at least one data string element is different from transmission frequency of the other data string element are regularly and periodically inserted.
The digital filtering circuit of the second configuration comprises a delay line composed of (f1/f2)xc3x97(Nxe2x88x921) D flip-flops, where f1 is transmission frequency of the data string, f2 is transmission frequency of a data string element whose transmission frequency is least among the data string elements contained in the data string and N is a number of taps; a plurality of selecting means for selecting and outputting one out of two or more taps other than a center tap among the plurality of taps of the delay line; a plurality of multipliers for multiplying output data of the plurality of selecting means and data of the center tap by coefficients, respectively; and an adder for adding outputs of the multipliers.
The delay line is operated with the transmission frequency f1 of the data string. Meanwhile, the selecting means process the plurality of data string elements by switching the taps connected to the multipliers so that the interval between the taps becomes f1/f3 of D flip-flops based on the center tap, where f1 is the transmission frequency of the data string and f3 is the transmission frequency of the data string element to which data outputted to the center tap at the time selected by the selecting means belongs.
By constructing as described above, the D flip-flops are operated with the frequency of the input data string when the data string elements are data of the luminance signal Y of 13.5 MHz and data of the color-difference signals Cr and Cb of 6.75 MHz and when the frequency of the data string in which the data of those data string elements are regularly and periodically inserted or multiplexed is f1=27 MHz. Then, the selector circuits as the selecting means switch the taps connected to the multipliers so that the intervals of the taps selected by the selector circuits is (frequency of the data string f1=27 MHz)/(frequency of the data string element to which data outputted to the center tap at that time belongs (f3=13.5 MHz in case of the luminance signal Y and f3=6.75 MHz in case of the color-difference signals Cb and Cr)) of the D flip-flops, i.e., two or four D flip-flops based on the center tap. That is, the plurality of multipliers and the adder within the digital filtering circuit may be used for filtering the luminance signal Y and the color-difference signals Cb and Cr in a time division manner by selectively switching the outputs of the D flip-flops connected with the multipliers by the selecting means. In other words, the plurality of multipliers and the adder within the digital filtering circuit are shared in filtering the luminance signal Y and the color-difference signals Cb and Cr. This means that the circuit scale of the digital filtering circuit may be reduced.
Accordingly, it is possible to reduce the cost of a semiconductor integrated circuit device as a result even when the digital filtering circuit constructed as described above is formed within the semiconductor integrated circuit device because of a decrease in an area occupied by the digital filtering circuit on a semiconductor chip on which the semiconductor integrated circuit device is formed.
A digital filtering circuit of a third configuration of the invention contains a first filtering circuit and a second filtering circuit for receiving an output of the first filtering circuit.
The first filtering circuit is the digital filtering circuit of the first configuration or the digital filtering circuit of the second configuration described above.
Meanwhile, the second filtering circuit is coupled so as to receive the output of the digital filtering circuit of the first or second configuration.
The second filtering circuit is a digital filtering circuit for filtering in a second direction to unit of data having a two-dimensional structure in which data of a plurality of data string elements of one line are regularly and periodically inserted or multiplexed in a first direction and data of the same data string element among the above-mentioned plurality of data string elements are arrayed in the second direction orthogonal to the first direction.
The second filtering circuit comprises a FIFO memory having a capacity for storing at least one line of the data string in the first direction, a plurality of multipliers for multiplying a plurality of taps which are set at an input of the FIFO memory and at the position of data interval of n lines (n is an integer of 1 or more) from the input of the FIFO memory by respective coefficients, and an adder for adding respective outputs of the plurality of multipliers. Then, the digital filtering circuit is arranged such that the FIFO memory is operated with the frequency of the data string and the process of the plurality of data string elements is performed in a time division manner.
In the digital filtering circuit of the third configuration, the first filtering circuit is a horizontal direction filtering circuit section and the second filtering circuit is a vertical direction filtering circuit section.
According to the configuration described above, the plurality of multipliers and the adder of the first filtering circuit and the plurality of multipliers and the adder of the second filtering circuit are shared in filtering the luminance signal Y and the color-difference signals Cb and Cr.
Accordingly, the cost of the semiconductor integrated circuit device may be reduced as a result even when the digital filtering circuit of the third configuration is formed within the semiconductor integrated circuit device because an area occupied by the digital filtering circuit of the third configuration on the semiconductor chip on which the semiconductor integrated circuit device is formed is reduced.
The specific nature of the invention, as well as other objects, uses and advantages thereof, will clearly appear from the following description and from the accompanying drawings in which like numerals refer to like parts.